INTEGRATION OF NANOWIRES WITH CMOS SEMICONDUCTOR CHIPS

For fabrication of CMOS semiconductor chips optolithographic process has widely been used since the dawn of fabrication. It has proved its worth over the years and successfully outsmarts the other technologies which have been used in the silicon based industry.

Present CMOS chip fabrication process can go further down may be to 10 nm. To fabricate CMOS chips of such a size range with such high precision and accuracy call for expensive equipments. The best way to go further down is to deviate from optolithographic process to self aligning nano elements called nanowires or nanotubes. Semiconductor industry is not ready to abruptly dump the lithography based equipment for nanowire based process due to cost and strategic reasons.

That’s why researchers are working out a smooth transition from the present CMOS to nano-element based by initially combining both methods and use much of the present technologies for some time at least in moving over to a totally different process.

Silicon, being abundant and most affordable metal will stay during the transition. So the challenge for the nano-technology researchers is to commercialize their Nano technology idea by effectively using present CMOS process, Silicon and its friends.

Few breakthrough in this direction from researchers around the world were noticed:

France based nano technology researcher Leti got step closer to integrating Silcon nanowires into traditional CMOS semiconductor chip making process.

Leti researchers have created silicon nanowire at temperature of 400˚C by using a copper-based catalyst using a method different from normal. The highlight of the research is that they could generate nano devices at low temperature of 400˚C which is far less than what others are achieved. Most of Silicon based nanowires were made in the temperature of 600˚C to 1000˚C inside a furnace. Another highlight is that researchers have created nanowires on oxidized metals.

Achieving at temperature convenient for making CMOS semiconductor chips and on oxide material brings Leti close to integrating nanowires on CMOS semiconductor chip. In this way future System-on-Chip (SoC) can house sensors and other nanotechnology based components mainly the Optoelectronic devices.

University of California, Berkeley has put on its website a report of its research work of growing Au-catalyzed vapor-liquid-solid nanowire via metal-organic chemical vapor deposition. It state "The nanoneedles grow on GaAs, silicon and sapphire substrates and exhibit bright room-temperature photoluminescence. The growths are conducted at 380 to 420 °C, making the process ideal for silicon-CMOS integration".

In another development researchers at Stanford University have developed method of stacking and crystalline semiconductor layers that sets the potential for three-dimensional microchips.

Due to their high surface-to-volume ratio, nanowires are highly suitable for the electrical detection of chemical or biological substances, converting solar to electrical energy and in developing high energy storing batteries. The immediate applications of nanowire integrated CMOS chips are in health, environment and solar energy conversion. Consequently energy generation will become far easier.